Various known semiconductor components (including associated integrated circuits) possess a thin, monocrystalline silicon layer which layer is applied to an insulating substrate which serves as carrier. Various techniques are known to the art for the production of such semiconductor components. For example, in accordance with the so-called SOS technique, a monocrystalline silicon layer is applied by deposition to a substrate crystal, such as a spinel or a sapphire. For another example, the so-called "dielectric insulation technique" utilizes a dielectric carrier layer having a thickness of a few microns and consisting of, for instance, SiO.sub.2, deposited on the surface of, for instance, a monocrystalline silicon wafer. The resulting silicon wafer is then thinned to a desired dimension, the thinning being effected by polishing, etching, or the like. A disadvantage of the first-mentioned technique is that the silicon layers produced by hetero-epitaxy contain more interference centers or crystal imperfections than the producible solid or bulk monocrystalline silicon. The properties of the boundary between the silicon layer and the insulating substrate, furthermore, give rise to various limitations. The "dielectric insulation" technique suffers from various disadvantages, particularly the relatively high outlay for the application of an insulating, dielectric carrier layer.